SME Hiring Andruews-LTTS

Memory

 

  1. Knowledge on Memory Trainings with respect to Servers
  2. Knowledge on Memory paging policies
  3. In depth knowledge on different memory generation and sub-components
  4. Different memory configs its advantage and dis-advantages
  5. Good Knowledge on Server booting sequence, UMA/NUMA , hyper-threading, caching, COD, processor turbo operation, processor, memory,
  6. Strong working knowledge on Memory Overflow, Memory Overclocking, Memory Library Operation
  7. Good Knowledge on Installation and configuration of Linux server operating systems
  8. Familiar with industry standard hypervisors  such as HyperV, Xen, KVM, and ESX.  Can create, configure, and restore, and migrate VMs.
  9. Understands advanced virtualization technologies such as topics of SMDQ, SRIOV, VT-d.  Understands the role of virtualization in the enterprise and in the cloud.
  10. Understand the Buffer Memory Overflow and LV memory overflow
  11. Familiarity with Memory Accesses Categories
  12. Good Knowledge of using kernel debugge Familiar with industry standard benchmarks such as stream, lmbench, linpack,  specpower, speccpu,  specjenterprise, and MLC
  13. Good Understands the contribution of system elements to overall system power.  Understands power measurements taken from silicon for memory, processor, and power supply.
  14. Good Understand of the operating systems and tools.  Ability to generate traffic using toolset and measure throughput against theoretical calculations.  Understands different data traffic patterns in the server

 

 

PCIe Sub System

 

  • Familiarity SOC Architecture and Design.
  • Experience in Silicon validation using functional and requirement based validation methodologies
  • Knowledge of Board hardware and Schematic
  • Familiarity with IPC (inter processor communication), Message Queues, DMA, Timers, Watchdog Timers and other IPs
  • Knowledge of industry standard interfaces like PCIe, USB, SDIO and MIPI standards are highly desirable
  • Checking of UPI Link Speed, Link State & Link lanes with fully populated IO devices on the platform
  • Validating UPI health check, UPI topology with Multiple power states and CPU Socket communications
  • Validating Virtualization Hyper-V features with multiple scenarios (i.e, VT-D PCIe passthrough on NVMe drivers, VT-D PCI Passthrough on Network Ports)
  • Performing all Hotplug scenarios and Different types of Error injections using PCIe devices
  • Applying the stress with Mixed UPI Speed & Default UPI Speed using different types of stress tools
  • Verifying the IOE/PCIe devices in IOE & Spare mode with all power cycles for Legacy and Non-Legacy IO Devices
  • Experience in using lab equipments such as Oscilloscopes, Protocol Analyzers/ Exercisers, Logic Analyzers, JTAG based Debuggers etc.
  • Familiarity with CPU architecture (ARM, ARC, MIPS), embedded systems desired
  • Work with Design, FW, and Validation teams to debug any issues found and find root cause on failure cases
  • Hands-on role must be comfortable with hardware, software, and lab test equipment.
  • Participating in meetings and understanding/developing the Validation strategy.
  • Hands on experience on OS flavors Windows, Linux CentOS and RHEL OS.
  • Ability to understand existing scripts in Python and write new scripts/make changes to Python based validation and debug scripts.
  • Manage team utilization, Excellent oral and written communication skills

 

Networking Sub System

 

  • Familiarity with CPU architecture (ARM, ARC, MIPS), embedded systems desired
  • Knowledge of Board hardware and Schematic
  • Familiarity with IPC (inter processor communication), Message Queues, DMA, Timers, Watchdog Timers and other IPs
  • End-to-end trouble isolation and repair on physical and logical layer services
  • Strong switch, router, modem knowledge and ability to setup, configure the devices upgrade firmware
  • Strong understanding of infrastructure protocols (BGP, IS-IS, VRRP, ), IP addressing and application protocols (HTTP/S, LDAP, SNMP)
  • Expert level knowledge in all the support tools required to support such environments, dig, host, nslookup, tcpdump, wiresha
  • LAN troubleshooting/problem determination skills (Ethernet, Hot Standby Router Protocol (HSRP), Enhanced Interior Gateway Routing Protocol (EIGRP),Border Gateway Protocol
  • IP services, , IP, Multicast, Quality of Service (QOS), Simple Network Management Protocol (SNMP)
  • Experience management gateways and Domain Name Services (DNS)
  • Strong working knowledge in networks, protocols and Internet technologies such as routing, NAT, advanced TCP/IP
  • Should have a good understanding of system power/reset/boot flows, and firmware (BIOS, BMC and CPLD, etc.) interactions during the process
  • Familiarity SOC Architecture and Design.
  • Hands on experience on OS flavors Windows, Linux CentOS and RHEL OS.
  • Hands-on role must be comfortable with hardware, software, and lab test equipment.
  • Experience in Silicon validation using functional and requirement based validation methodologies
  • Knowledge of system architecture, Must work independently, be proactive

 

Multisocket Sub System

 

  • Good Knowledge on Server Platform Architecture and UPI Ultra Path Interconnect
  • Knowledge of Board hardware and Schematicm.
  • Hands on experience on 2Socket, 4Socket and 8Socket server platform with flashing Software Ingredients i.e. IFWI, BMC, CPLD and Voltage Regulator
  • Good Knowledge on Spare mode and PCH IOE mode
  • Good Knowledge on converting 4S to 2S and Vice versa and 8S to 2S and Vice versa
  • Good Knowledge on analyzing Mesh and Ring Topology and verifying the Link speed from lower to higher speed
  • Good Knowledge on Memory configuration 1DPS, 1DPC and 2DPC
  • Good understanding on failure verification and Debug and live debugging
  • Hands on experience on OS flavors Windows, Linux CentOS and RHEL OS, VM Ware OS
  • Good understanding on Multisocket Configurations for 4Socket and 8Socket
  • Familiarity with IPC (inter processor communication), Message Queues, DMA, Timers, Watchdog Timers and other IPs
  • Familiarity with CPU architecture (ARM, ARC, MIPS), embedded systems desired
  • Participating in meetings and understanding/developing the Validation strategy.

 

 

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Job Code
JPC - 1695
Posted Date
2023-05-17 04:08:59
Experience
10-15 years
Primary Skills
memory